1. Field of the Invention
The present invention relates to a memory cell circuit, and more particularly, it relates to a multiport memory which has independently accessible write and read ports.
2. Description of the Prior Art
A. Prior Art
(A-1) First Prior Art
FIG. 32 is a circuit diagram showing an exemplary structure of a memory cell circuit 17a of a conventional multiport memory having a single write port and a single read port. A memory circuit 21 is formed by a flip-flop circuit having inverter circuits 14a and 14b whose output terminals 201a and 201b are connected to input terminals of the inverter circuits 14b and 14a respectively. Thus, data stored in the memory circuit 21 complementarily appear at the output terminals 201a and 201b of the inverter circuits 14a and 14b.
FIGS. 33 and 34 are diagrams illustrating the structure and the operation of an inverter circuit 14 shown in FIG. 32 as inverters 14a-c. FIG. 33 is a logic symbol diagram of the inverter circuit 14, and FIG. 34 illustrates the inverter circuit 14 which is formed by MOS transistors.
Referring to FIG. 34, gates and drains of a P-channel MOS transistor 51 and an N-channel MOS transistor 52 are connected in common respectively. A power supply line 111 is connected to a source of the transistor 51, to supply a VDD potential. On the other hand, a grounding conductor 112 is connected to a source of the transistor 52, to supply a GND potential. An input terminal 202 of the inverter circuit 14 having such a structure is connected with the gates of the transistors 51 and 52 in common, while its output terminal 201 is connected with the drains of the transistors 51 and 52 in common.
When low-level data, i.e., the GND potential is supplied to the input terminal 202 of the inverter circuit 14, the transistor 51 enters a conducting state and the transistor 52 enters a cutoff state, so that the output terminal 201 is driven at the VDD potential. When high-level data, i.e., the VDD potential is supplied to the input terminal 202, on the other hand, the transistor 51 enters a cutoff state and the transistor 52 enters a conducting state, so that the output terminal 201 is driven at the GND potential. Namely, the output terminal 201 outputs low-level data which is reverse to the received high-level data.
Referring again to FIG. 32, an input of the inverter circuit 14b goes low and its output goes high if an output of the inverter circuit 14a is at a low level, for example. Namely, the terminals 201a and 201b of the memory circuit 21 go low and high respectively. Thus, it is possible to hold data in the terminals 201a and 201b of the memory circuit 21, which is formed by a flip-flop circuit.
The aforementioned memory circuit 21 is provided with write access gates for writing data supplied in the write port, to be connected with write bit lines 191a and 191b for transferring write data and a write word line 181 for selecting a desired memory cell circuit.
The write access gates are formed by N-channel MOS transistors 13a and 13b. The transistor 13a has a drain which is connected to the terminal 201a of the memory circuit 21, a source which is connected to the write bit line 191a, and a gate which is connected to the write word line 181. Similarly, the transistor 13b has a drain which is connected to the other terminal 201b of the memory circuit 21, a source which is connected to the write bit line 191b, and a gate which is connected to the write word line 181.
Further, a read buffer circuit 22a is provided for reading the data stored in the memory circuit 21, and connected with a read bit line 192 for transferring data to be read and a read word line 184 for selecting a desired memory cell circuit.
The read buffer circuit 22a is formed by an inverter circuit 14c having an input terminal 202c and an output terminal 201c, and an N-channel MOS transistor 50 which is a read access gate. The transistor 50 has a drain which is connected to the output terminal 201c of the inverter circuit 14c, a source which is connected to the read bit line 192, and a gate which is connected to the read word line 184. The input terminal 202c of the inverter circuit 14c is connected to the terminal 201b of the memory circuit 21 to connect the read buffer circuit 22a with the memory circuit 21, thereby forming the memory cell circuit 17a.
The operation of the aforementioned memory cell circuit 17a is now described. In order to write data, a write driver circuit (not shown) which is connected to the bit lines 191a and 191b is so employed as to drive the bit lines 191a and 191b to low and high levels in response to the value of the data to be written. At this time, the bit lines 191a and 191b are supplied with logical levels which are complementary to each other. In other words, the bit line 191b is driven to a high level when the bit line 191a is driven to a low level, and vice versa.
Thereafter the word line 181 is converted to a high level, thereby bringing the access gates 13a and 13b into conducting states. Thus, the terminals 201a and 201b of the memory circuit 21 holding the data are electrically connected with the bit lines 191a and 191b respectively.
Thus, logical levels at the terminals 201a and 201b of the memory circuit 21 are equalized to those supplied to the bit lines 191a and 191b respectively regardless of the logical level of the held data. The write operation is thus completed.
When the word line 181 is converted to a low level after the completion of the write operation, the access gates 13a and 13b are so cut off that the memory circuit 21 holds the written data. Even if the values of the bit lines 191a and 191b are thereafter changed, the logical level of the held data remains unchanged since the bit lines 191a and 191b are not electrically connected with the memory circuit 21.
Description is now made on a data read operation. The word line 184 is so converted to a high level that the access gate 50 enters a conducting state. Thus, the output terminal 201c of the inverter circuit 14c forming the read buffer circuit 22a is electrically connected with the bit line 192, so that the logical level which is supplied to the bit line 192 is driven to a logical level which is supplied to the terminal 201c, i.e., a logical level complementary to that of the data stored in the terminal 201b of the memory circuit 21.
The bit line 192 is connected with a sense amplifier circuit (not shown) directly or through a transfer gate, so that the data read on the bit line 192 is driven to a circuit of a next stage. The read operation is completed in the aforementioned manner.
When the word line 184 is converted to a low level after the completion of the read operation, the access gate 50 enters a cutoff state so that the bit line 192 is electrically cut off from the read buffer circuit 22a.
Thus, the read buffer circuit 22a is so provided in the memory cell circuit 17a as to prevent the memory data from destruction by the read operation. Further, it is possible to simultaneously perform read and write operations since the data are read and written from independent ports.
(A-2) Second Prior Art
FIG. 35 is a circuit diagram showing another conventional memory cell circuit 17b having a read buffer circuit 22b, which is provided with a CMOS transistor pair in place of the access gate 50 provided in the read buffer circuit 22a shown in FIG. 32.
The circuit structure of this memory cell circuit 17b is now described. A memory circuit 21 is formed in a similar manner to that shown in FIG. 32. The read buffer circuit 22b is formed by an inverter circuit 14c, and read access gates which are defined by a P-channel MOS transistor 54 and an N-channel MOS transistor 53.
The transistors 53 and 54 have drains which are connected to an output terminal 201c of the inverter circuit 14c in common, and sources which are connected to a read bit line 192 in common. The transistors 53 and 54 further have gates which are connected to read word lines 184 and 185 respectively.
An input terminal 202c of the inverter circuit 14c is connected to a terminal 201b of the memory circuit 21 to connect the memory circuit 21 with the read buffer circuit 22b, thereby forming the memory cell circuit 17b.
A data write operation of the aforementioned memory cell circuit 17b is identical to that of the first prior art. As to a data read operation, on the other hand, the read word lines 184 and 185 are in a complementary relation to each other for transferring non-inversion and inversion signals respectively. The word lines 184 and 185 are converted to high and low levels respectively, so that the access gates 53 and 54 enter conducting states.
Thus, the output terminal 201c of the inverter circuit 14c forming the read buffer circuit 22b is electrically connected to the bit line 192, so that a logical level which is supplied to the bit line 192 is driven to a logical level which is supplied to the terminal 201c, i.e., that complementary to the logical level of data stored in the terminal 201b of the memory circuit 21.
The bit line 192 is connected with a sense amplifier circuit (not shown) directly or through a transfer gate, so that data read on the bit line 192 is driven to a circuit of a next stage. The read operation is completed in the aforementioned manner.
After the completion of the read operation, the word lines 184 and 185 are converted to low and high levels respectively, whereby the access gates 53 and 54 enter cutoff states and the bit line 192 is electrically cut off from the read buffer circuit 22b.
(A-3) Third Prior Art
FIG. 36 is a circuit diagram showing a modification of the memory cell circuit 17b according to the second prior art. The circuit structure of this memory cell circuit 17c is now described. A memory circuit 21 has the same structure as that of the first prior art. A read buffer circuit 22c is formed by P-channel transistors 55 and 56 and N-channel MOS transistors 57 and 58.
A source of the transistor 56 and a drain of the transistor 55 are connected in common while a source of the transistor 55 is connected to a power supply line 111 to be supplied with a VDD potential. A source of the transistor 57 and a drain of the transistor 58 are connected in common, while the source of the transistor 57 is connected to a grounding conductor 112 to be supplied with a GND potential. Gates of the transistors 55 and 58 are connected in common to form the read buffer circuit 22c.
Gates of the transistors 57 and 56 are connected to word lines 184 and 185 respectively. The gates of the transistors 55 and 58 are connected to the terminal 201b of the memory circuit 21 in common to connect the memory circuit 21 with the read buffer circuit 22c, thereby forming the memory cell circuit 17c.
A data write operation of the memory cell circuit 17c is identical to that of the first prior art. As to a data read operation, on the other hand, the read word lines 184 and 185 are in a complementary relation to each other for transferring non-inversion and inversion signals respectively similarly to the second prior art. The word lines 184 and 185 are converted to high and low levels respectively, so that the transistors 56 and 57 enter conducting states.
If a logical level which is supplied to the terminal 201b of the memory circuit 21 is at a low level, the transistors 55 and 58 enter conducting and cutoff states respectively. Namely, a bit line 192 is driven to the VDD potential, so that high-level data is read.
When the transistors 56 and 57 are in conducting states and the terminal 201b of the memory circuit 21 is at a high level, on the other hand, the transistors 55 and 58 enter cutoff and conducting states respectively. Namely, the bit line 192 is driven to the GND potential, so that low-level data is read.
The bit line 192 is connected with a sense amplifier circuit (not shown) directly or through a transfer gate, so that the data read on the bit line 192 is driven to a circuit of a next stage. The read operation is completed in the aforementioned manner.
After the completion of the read operation, the word lines 184 and 185 are converted to low and high levels, so that the transistors 56 and 57 enter cutoff states and the bit line 192 is electrically cut off from the read buffer circuit 22c.
The memory cell circuit 17a according to the first prior art is adapted to read both high and low level data with a single read bit line 184. However, it is impossible to completely transfer high-level data since the read access gate is formed only by the N-channel MOS transistor 50.
When high-level data is read, the potential of the read bit line 192 can be driven through the N-channel MOS transistor 50 merely to a level which is reduced from the VDD potential by the threshold value of the MOS transistor 50 even if the output of the inverter circuit 14c of the read buffer circuit 22a is at the VDD potential (high level).
Due to such incomplete transfer of the VDD potential, a sufficient operation margin cannot be ensured as a source voltage supplying the VDD potential is reduced, leading to a malfunction as the case may be. Namely, the first prior art has such a first problem that a logical level which is reverse to that of the data stored in the memory circuit 21 may be disadvantageously driven to the circuit of the next stage even if high-level data is read, since the potential supplied to the bit line 192 cannot be completely raised up to the VDD potential.
When high-level data is read on the read bit line 192, further, the read bit line 192 is driven by the P-channel MOS transistor 51 forming the inverter circuit 14c, while a delay at the P-channel MOS transistor 50 serving as an access gate is inevitably added to the access time since the bit line 192 is driven through the transistor 50. Namely, the first prior art has such a second problem that the transistor 50 hinders reduction of the access time.
The second prior art is so structured as to solve the first problem. Namely, access gates are defined by transfer gates formed by a CMOS transistor pair employing both P-channel and N-channel MOS transistors 54 and 53.
When high-level data is read on the read bit line 192, therefore, the read bit line 192 is completely driven to the VDD potential to cause no problem as to the operation margin. However, the bit line 192 is driven through the access gates similarly to the first prior art, to result in the second problem of the unnecessary increase of the access time caused by delays in the access gates.
The operation margin is improved also in the third prior art. In this case, however, the two transistors are connected in series between the VDD or GND potential and the bit line 192, to lead to a long delay time.
When high-level data is read on the read bit line 192, the read bit line 192 is driven to the VDD potential through the P-channel MOS transistors 55 and 56. The above problem is particularly remarkable in this case since the operating speed of a P-channel MOS transistor is generally slower than that of an N-channel MOS transistor.
Thus, each of the conventional memory cell circuits has the following problems in relation to a read operation:
(1) A stable read operation cannot be performed since it is impossible to ensure a sufficient operation margin. PA1 (2) A delay time in a read buffer circuit for driving a bit line is so large that an access time is retarded.